Ram memory device selectively protectable with ecc

Abstract

An SRAM memory device including a plurality of memory cells arranged in a plurality of rows and a plurality of columns; each row of memory cells is adapted to store a RAM word; the RAM word includes a corresponding data word, a corresponding ECC word to be used for error detection and correction purposes and a corresponding applicative word to be used during debugging operations. The SRAM memory device further includes a configurable port adapted to receive a RAM word and to program corresponding memory cells of a selected row based on the received RAM word during a writing access of the SRAM memory device. The SRAM memory device further includes a memory controller unit including circuitry for selectively configuring the configurable port in one among a plurality of modes. The plurality of modes includes a first mode, wherein the configurable port is configured in such a way to disable the programming of the data word and of the corresponding ECC word of the received RAM word and at the same time enable the programming of the applicative word of the received RAM word during the writing access. The plurality of modes includes a second mode, wherein the configurable port is configured in such a way to disable the programming of the applicative word of the received RAM word and at the same time enable the programming of the data word and of the corresponding ECC word of the received RAM word during the writing access.