The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2013

Filed:

Jan. 18, 2011
Applicants:

Rolf Van DE Burgt, Oosterbeek, NL;

Bernd Elend, Hamburg, DE;

Inventors:

Rolf van de Burgt, Oosterbeek, NL;

Bernd Elend, Hamburg, DE;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); G06F 1/00 (2006.01); G06F 1/04 (2006.01); G06F 15/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

Various embodiments relate to a network receiver using distributed clock synchronization. The network receiver may include a first timing engine that samples bits received by the receiver with a first clock having a first clock frequency (f) with a first clock frequency tolerance (Δf), and a second timing engine that samples bits received by the receiver with a second clock having a second clock frequency (f) with a second clock frequency tolerance (Δf). The second clock frequency is less than the first clock frequency. The network receiver may also include a third timing engine that samples bits received by the receiver with a third clock having a third clock frequency (f) with a third clock frequency tolerance (Δf). The third clock frequency may be greater than the first clock frequency. The network receiver may also include a timing engine resolver that determines which of the first, second, and third timing engines correctly samples the bits received by the receiver; wherein f−Δf<f+Δf; wherein f−Δf<f+Δf.


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