The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2013
Filed:
Dec. 30, 2011
Suresh Natarajan Rajan, San Jose, CA (US);
Keith R. Schakel, San Jose, CA (US);
Michael J. S. Smith, Palo Alto, CA (US);
David T. Wang, Thousand Oaks, CA (US);
Frederick Daniel Weber, San Jose, CA (US);
Suresh Natarajan Rajan, San Jose, CA (US);
Keith R. Schakel, San Jose, CA (US);
Michael J. S. Smith, Palo Alto, CA (US);
David T. Wang, Thousand Oaks, CA (US);
Frederick Daniel Weber, San Jose, CA (US);
Google Inc., Mountain View, CA (US);
Abstract
A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.