The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2013
Filed:
Jan. 23, 2012
Xiaohong Quan, San Diego, CA (US);
Tongyu Song, San Diego, CA (US);
Lennart Mathe, San Diego, CA (US);
Dinesh J. Alladi, San Diego, CA (US);
Xiaohong Quan, San Diego, CA (US);
Tongyu Song, San Diego, CA (US);
Lennart Mathe, San Diego, CA (US);
Dinesh J. Alladi, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. A non-overlapping clock generation circuit comprises a delay lock loop (DLL) circuit that generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. The clock generator circuit may also include voltage-controlled delay cells that generate sets of clock signals delayed from one another by a non-overlapping time (t).