The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2013
Filed:
Dec. 06, 2011
Nathan Buck, Underhill, VT (US);
Brian Dreibelbis, Underhill, VT (US);
John P. Dubuque, Jericho, VT (US);
Eric A. Foreman, Fairfax, VT (US);
James C. Gregerson, Hyde Park, NY (US);
Peter A. Habitz, Hinesburg, VT (US);
Jeffrey G. Hemmett, St. George, VT (US);
Debjit Sinha, Wappingers Falls, NY (US);
Natesan Venkateswaran, Hopewell Junction, NY (US);
Chandramouli Visweswariah, Croton-on-Hudson, NY (US);
Michael H. Wood, Hopewell Junction, NY (US);
Vladimir Zolotov, Putnam Valley, NY (US);
Nathan Buck, Underhill, VT (US);
Brian Dreibelbis, Underhill, VT (US);
John P. Dubuque, Jericho, VT (US);
Eric A. Foreman, Fairfax, VT (US);
James C. Gregerson, Hyde Park, NY (US);
Peter A. Habitz, Hinesburg, VT (US);
Jeffrey G. Hemmett, St. George, VT (US);
Debjit Sinha, Wappingers Falls, NY (US);
Natesan Venkateswaran, Hopewell Junction, NY (US);
Chandramouli Visweswariah, Croton-on-Hudson, NY (US);
Michael H. Wood, Hopewell Junction, NY (US);
Vladimir Zolotov, Putnam Valley, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA.