The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2013
Filed:
Feb. 20, 2008
Guojun Ren, San Jose, CA (US);
Prasad Rau, Campbell, CA (US);
GuoJun Ren, San Jose, CA (US);
Prasad Rau, Campbell, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method for automating input/output buffer information specification (IBIS) model generation. A wrapper utility combines components into an automated generation flow to model multiple input/output (I/O) buffers that conform to single-ended and differential I/O standards. Configuration data files are imported to properly configure the modeled I/O buffers according to a specific set of signal parameters across all process corners. Output and input termination impedance may also be modeled within the I/O buffer. A simulation setup file of the modeled I/O buffer is generated to determine the voltage/current (V/I) and voltage/time (V/T) data for the modeled I/O buffer for each process corner. A raw IBIS model is then created, formatted, and validated to determine the accuracy of the IBIS model. Execution steps of the IBIS model generator are then iterated to automatically generate, correlate, and compile IBIS models for each I/O standard into a single file.