The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2013
Filed:
Dec. 05, 2007
Kenneth V. Buer, Gilbert, AZ (US);
Gaurav Menon, Gilbert, AZ (US);
Ramanamurthy V. Darapu, Gilbert, AZ (US);
Dean Muellenberg, Tempe, AZ (US);
Kenneth V. Buer, Gilbert, AZ (US);
Gaurav Menon, Gilbert, AZ (US);
Ramanamurthy V. Darapu, Gilbert, AZ (US);
Dean Muellenberg, Tempe, AZ (US);
ViaSat, Inc., Carlsbad, CA (US);
Abstract
Systems, devices and methods are disclosed for suppressing the 2LO frequency spur, output from a mixer. In various exemplary embodiments, a DC bias circuit is electrically connected to provide DC bias to one or more non-linear elements of the mixer. The biasing voltage is used to cause the current-voltage characteristics and/or junction capacitances between non-linear elements to be more symmetric and/or to suppress 2LO leakage currents that form 2LO frequency spurs at the output of the mixer. The non-linear elements may comprise one of: BJT's, diodes, and FET's. The mixer may be one of: a subharmonic mixer; a fundamental resistive mixer; a fundamental subharmonic transconductance mixer; and a fundamental transconductance mixer comprising an anti-parallel diode pair. The system may further be configured to automatically determine an appropriate DC bias voltage level that will improve one of the LO-IF isolation and the LO-RF isolation.