The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2013
Filed:
Jul. 05, 2012
Yong-ho Jang, Gyeonggi-do, KR;
Seung-chan Choi, Gyeonggi-do, KR;
Jae-yong You, Seoul, KR;
Woo-seok Choi, Gyeonggi-do, KR;
Yong-Ho Jang, Gyeonggi-do, KR;
Seung-Chan Choi, Gyeonggi-do, KR;
Jae-Yong You, Seoul, KR;
Woo-Seok Choi, Gyeonggi-do, KR;
LG Display Co., Ltd., Seoul, KR;
Abstract
Disclosed herein is a gate driving circuit including a first clock generator to sequentially output n output clock pulses, a second clock generator to sequentially output n output control clock pulses, and a shift register to receive the n output clock pulses and the n output control clock pulses and to sequentially output a plurality of scan pulses, wherein high sections of k-th to (k+s)-th output clock pulses output during adjacent periods overlap with one another, a k-th output control clock pulse rises before the k-th output clock pulse, the k-th output control clock pulse falls before a (k−a)-th output clock pulse, a high section of the output control clock pulses does not overlap with that of the k-th output clock pulse, and a (k+b)-th output clock pulse falls during the high section of the output control clock pulses not overlapping with that of the k-th output clock pulse.