The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2013
Filed:
Apr. 18, 2011
Applicants:
Po-shen Lai, San Jose, CA (US);
Paul A. Lassa, Mountain View, CA (US);
Paul C. Paternoster, Los Altos, CA (US);
Inventors:
Po-Shen Lai, San Jose, CA (US);
Paul A. Lassa, Mountain View, CA (US);
Paul C. Paternoster, Los Altos, CA (US);
Assignee:
SanDisk Technologies Inc., Plano, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3187 (2006.01); G01R 31/02 (2006.01); G01R 31/28 (2006.01); G01R 31/319 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2884 (2013.01); G01R 31/31924 (2013.01); G01R 31/318511 (2013.01);
Abstract
A multi-interface integrated circuit in which, during the chip's lifetime in use, only one interface is active at a time. However, special test logic powers up all of the on-chip interface modules at once, so that a complete test cycle can be performed. All of the interfaces are exercised in one test program. Since some pads are inactive in some interface modes, mask bits are used to select which pads are monitored during which test cycles.