The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2013

Filed:

Dec. 14, 2011
Applicants:

Nikhil Vishwanath Kelkar, Saratoga, CA (US);

Sagar Pushpala, Sunnyvale, CA (US);

Seshasayee Ss. Ankireddi, San Jose, CA (US);

Inventors:

Nikhil Vishwanath Kelkar, Saratoga, CA (US);

Sagar Pushpala, Sunnyvale, CA (US);

Seshasayee sS. Ankireddi, San Jose, CA (US);

Assignee:

Intersil Americas Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device is provided and includes a semiconductor die, and a plurality of bond pads having exposed surfaces arranged in an alternating interleaved pattern on the semiconductor die. Each of the surfaces of the bond pads have a first bond placement area that overlaps with a second bond placement area, with the first bond placement area having a major axis that is orthogonal to a major axis of the second bond placement area. A connecting bond is located at an intersection of the major axes of the first bond placement area and the second bond placement area on one or more of the bond pads.


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