The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2013

Filed:

Sep. 23, 2011
Applicants:

Jaeman Yoon, Seoul, KR;

Yungi Kim, Gyeonggi-do, KR;

Kangyoon Lee, Gyeonggi-do, KR;

Youngwoong Son, Gyeonggi-do, KR;

Inventors:

Jaeman Yoon, Seoul, KR;

Yungi Kim, Gyeonggi-do, KR;

Kangyoon Lee, Gyeonggi-do, KR;

Youngwoong Son, Gyeonggi-do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

An interconnection architecture, for a semiconductor device (having regions arranged to include at least an inner region, an intermediate region located at least aside the inner region, and an outer region located at least on a side of the intermediate region opposite to the inner region, includes: one or more pairs of first and second signal lines, each pair extending from the inner region into the intermediate region; first portions and second portions of the first and second signal lines being parallel, respectively, the first portions being located in the inner region; the first and second portion of at least the first signal line not being collinear; and an intra-pair line-spacing, d(i), for each pair including the following magnitudes, din the inner region, and d' in the intermediate region, where d<d


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