The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2013
Filed:
Jun. 02, 2011
Xiaoping Tang, Mohegan Lake, NY (US);
Michael S. Gray, Fairfax, VT (US);
Xin Yuan, Roseville, CA (US);
Xiaoping Tang, Mohegan Lake, NY (US);
Michael S. Gray, Fairfax, VT (US);
Xin Yuan, Roseville, CA (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Solutions for optimizing an integrated circuit layout for implementation in an integrated circuit are disclosed. In one embodiment, a computer-implemented method is disclosed including: obtaining a plurality of hierarchical constraints in mathematical form, the plurality of hierarchical constraints defining a first integrated circuit layout; partitioning the plurality of hierarchical constraints into groups according to one or more partitioning rules; determining whether a boundary condition exists between two of the groups, and distributing a slack or a gap between the two of the groups in the case that the boundary condition exists; creating a plurality of integer linear programming problems associated with each of the groups; determining a solution for each of the plurality of integer linear programming problems; and integrating each solution together to form a second integrated circuit layout.