The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2013
Filed:
Oct. 23, 2008
Robert Michael Muchsel, Addison, TX (US);
Donald W. Loomis, Coppell, TX (US);
Edward Tang K. MA, Plano, TX (US);
Mark Alan Lovell, Lucas, TX (US);
Michael Anthony Quarles, Canton, GA (US);
Robert Michael Muchsel, Addison, TX (US);
Donald W. Loomis, Coppell, TX (US);
Edward Tang K. Ma, Plano, TX (US);
Mark Alan Lovell, Lucas, TX (US);
Michael Anthony Quarles, Canton, GA (US);
Maxim Integrated Products, Inc., San Jose, CA (US);
Abstract
The present invention relates to a microcontroller designed for protection of intellectual digital content. The microcontroller includes a secure CPU, a real-time cipher, and a user programmable multi-layer access control system for internal memory realized by programmable nonvolatile memory. Programmable nonvolatile memory allows in-system and in-application programming for the end user. The programmable nonvolatile memory is mainly used for program code and operating parameter storage. The multiple-layer access control is an integral part of the CPU, providing confidentiality protection to embedded digital content by controlling reading, writing, and/or execution of a code segment according to a set of user-programmed parameters. The cipher incorporates a set of cryptographic rules for data encryption and decryption with row and column manipulation for data storage. All cryptographic operations are executed in parallel with CPU run time without incurring additional latency and delay for system operation.