The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2013
Filed:
Dec. 20, 2010
Ramon Mangaser, Boston, MA (US);
Shefali Walia, Waltham, MA (US);
Edoardo Prete, Arlington, MA (US);
Jonathan P. Dowling, Austin, TX (US);
Gerald R. Talbot, Concord, MA (US);
Sharad N. Vittal, Acton, MA (US);
Ramon Mangaser, Boston, MA (US);
Shefali Walia, Waltham, MA (US);
Edoardo Prete, Arlington, MA (US);
Jonathan P. Dowling, Austin, TX (US);
Gerald R. Talbot, Concord, MA (US);
Sharad N. Vittal, Acton, MA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A decision feedback equalization (DFE) receiver and method are provided. The DFE receiver is configured to sample data bits from a data bus. The DFE receiver includes a data sampler configured to sample a current data bit from the data bus using one of a first, second and third voltage reference. The DFE receiver also includes multiplexing logic configured to select one of the first, second and third voltage references based on a prior data bus level. The wherein the first voltage reference is selected if the prior data bus level was a logic zero. The second voltage reference is selected if the prior data bus level was a logic one. The third voltage reference is selected if the prior data bus level was tri-state.