The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2013
Filed:
Feb. 16, 2012
Junichi Shimada, Shiga, JP;
Hidenori Shibata, Toyama, JP;
Tsutomu Fujii, Osaka, JP;
Hiromasa Fukazawa, Hyogo, JP;
Nobuyuki Iwauchi, Osaka, JP;
Takeya Fujino, Osaka, JP;
Junichi Shimada, Shiga, JP;
Hidenori Shibata, Toyama, JP;
Tsutomu Fujii, Osaka, JP;
Hiromasa Fukazawa, Hyogo, JP;
Nobuyuki Iwauchi, Osaka, JP;
Takeya Fujino, Osaka, JP;
Panasonic Corporation, Osaka, JP;
Abstract
Disclosed is a semiconductor device having a multilayer wiring structure, in which a dummy pattern is formed in a wiring void with favorable manufacturing efficiency. In a semiconductor device having a multilayer wiring structure, dummy pattern () is formed in relatively narrow wiring void (Area_S) so as to extend in a direction different from that of dummy patterns () formed in relatively wide wiring void (Area_S).