The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2013
Filed:
Jul. 07, 2011
Kiyotaka Tsuji, Osaka, JP;
Takumi Mikawa, Shiga, JP;
Kenji Tominaga, Kyoto, JP;
Panasonic Corporation, Osaka, JP;
Abstract
A non-volatile semiconductor memory device comprises a plurality of memory cell holes () formed through an interlayer insulating layer () at respective cross-points of a plurality of first wires () of a stripe shape and a plurality of second wires () of a stripe shape when viewed from above such that the memory cell holes () expose upper surfaces of the plurality of first wires, respectively, a plurality of dummy holes () formed on the plurality of first wires in the interlayer insulating layer such that the dummy holes reach the upper surfaces of the plurality of first wires, respectively, and stacked-layer structures formed inside the memory cell holes and inside the dummy holes, respectively, each of the stacked-layer structures including a first electrode () and a variable resistance layer (); an area of a portion of the first wire which is exposed in a lower opening of one of the dummy holes being greater than an area of a portion of the first wire which is exposed in a lower opening of one of the memory cell holes; and one or more of the dummy holes being formed on each of the first wires.