The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2013

Filed:

Dec. 04, 2010
Applicants:

Jung Hee Lee, Daegu-Si, KR;

Ki Sik Im, Daegu-Si, KR;

Jong Bong Ha, Daegu-Si, KR;

Inventors:

Jung Hee Lee, Daegu-Si, KR;

Ki Sik Im, Daegu-Si, KR;

Jong Bong Ha, Daegu-Si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/335 (2006.01); H01L 21/8232 (2006.01); H01L 21/339 (2006.01); H01L 21/00 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to an enhancement normally off nitride semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buffer layer on a substrate; forming a first nitride semiconductor layer on the buffer layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer; etching a gate region above the second nitride semiconductor layer up to a predetermined depth of the first nitride semiconductor layer; forming an insulating film on the etched region and the second nitride semiconductor layer; patterning a source/drain region, etching the insulating film in the source/drain region, and forming electrodes in the source/drain region; and forming a gate electrode on the insulating film in the gate region. In this manner, the present invention provides a method of easily implementing a normally off enhancement semiconductor device by originally blocking 2DEG which is generated under a gate region. In addition, the present invention provides an enhancement normally off power semiconductor device with a simple and efficient driving circuit in a HEMT device.


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