The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2013
Filed:
Jul. 20, 2012
Raymond Kong, San Jose, CA (US);
David A. Knol, Morgan Hill, CA (US);
Frederic Revenu, San Carlos, CA (US);
Dinesh K. Monga, Santa Clara, CA (US);
Raymond Kong, San Jose, CA (US);
David A. Knol, Morgan Hill, CA (US);
Frederic Revenu, San Carlos, CA (US);
Dinesh K. Monga, Santa Clara, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
In one embodiment, a method for propagating design constraints between a module and a module instance in a circuit design is provided. A port of the module and a port/pin of the circuit design are determined, between which constraints are to be propagated. The determination of the port/pin includes determining whether or not pin of the module instance corresponding to the port is directly connected to a top-level port of the circuit design. In response to determining that the pin is directly connected to a top-level port, the top-level port is selected as the port/pin. In response to determining that the pin is not directly connected to the top-level port, the pin is selected as the port/pin. Design constraints are propagated between the port and the selected port/pin. The propagated design constraints are stored in a storage device.