The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2013

Filed:

Nov. 19, 2010
Applicants:

Alfred L. Rodriguez, San Jose, CA (US);

Nicholas J. Possley, Gilroy, CA (US);

Kevin Boshears, San Jose, CA (US);

Austin H. Lesea, Los Gatos, CA (US);

Jameel Hussein, Sunnyvale, CA (US);

Inventors:

Alfred L. Rodriguez, San Jose, CA (US);

Nicholas J. Possley, Gilroy, CA (US);

Kevin Boshears, San Jose, CA (US);

Austin H. Lesea, Los Gatos, CA (US);

Jameel Hussein, Sunnyvale, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and systems mitigate a soft error in an integrated circuit. A map is stored in a memory, and the map specifies a criticality class for each storage bit in the integrated circuit. A mitigative technique is associated with each criticality class. The soft error is detected in a corrupted one of the storage bits. The mitigative technique is performed that is associated with the criticality class specified in the map for the corrupted storage bit.


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