The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2013
Filed:
Sep. 23, 2011
Satoru Ito, Suwa, JP;
Masahiko Moriguchi, Suwa, JP;
Kazuhiro Maekawa, Chino, JP;
Noboru Itomi, Nirasaki, JP;
Satoru Kodaira, Chino, JP;
Junichi Karasawa, Tatsuno-machi, JP;
Takashi Kumagai, Chino, JP;
Hisanobu Ishiyama, Chino, JP;
Takashi Fujise, Shiojiri, JP;
Satoru Ito, Suwa, JP;
Masahiko Moriguchi, Suwa, JP;
Kazuhiro Maekawa, Chino, JP;
Noboru Itomi, Nirasaki, JP;
Satoru Kodaira, Chino, JP;
Junichi Karasawa, Tatsuno-machi, JP;
Takashi Kumagai, Chino, JP;
Hisanobu Ishiyama, Chino, JP;
Takashi Fujise, Shiojiri, JP;
Seiko Epson Corporation, Tokyo, JP;
Abstract
An integrated circuit device includes first to Nth circuit blocks CBto CBN, a first interface region disposed along a fourth side and on the Dside of the first to Nth circuit blocks CBto CBN, and a second interface region disposed along a second side and on the Dside of the first to Nth circuit blocks CBto CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction Dover the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.