The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2013

Filed:

Jul. 07, 2011
Applicants:

Yun-mo Chung, Yongin, KR;

Ki-yong Lee, Yongin, KR;

Min-jae Jeong, Yongin, KR;

Jin-wook Seo, Yongin, KR;

Jong-won Hong, Yongin, KR;

Heung-yeol NA, Yongin, KR;

Eu-gene Kang, Yongin, KR;

Seok-rak Chang, Yongin, KR;

Tae-hoon Yang, Yongin, KR;

Ji-su Ahn, Yongin, KR;

Young-dae Kim, Yongin, KR;

Byoung-keon Park, Yongin, KR;

Kil-won Lee, Yongin, KR;

Dong-hyun Lee, Yongin, KR;

Sang-yon Yoon, Yongin, KR;

Jong-ryuk Park, Yongin, KR;

Bo-kyung Choi, Yongin, KR;

Maxim Lisachenko, Suwon-si, KR;

Inventors:

Yun-Mo Chung, Yongin, KR;

Ki-Yong Lee, Yongin, KR;

Min-Jae Jeong, Yongin, KR;

Jin-Wook Seo, Yongin, KR;

Jong-Won Hong, Yongin, KR;

Heung-Yeol Na, Yongin, KR;

Eu-Gene Kang, Yongin, KR;

Seok-Rak Chang, Yongin, KR;

Tae-Hoon Yang, Yongin, KR;

Ji-Su Ahn, Yongin, KR;

Young-Dae Kim, Yongin, KR;

Byoung-Keon Park, Yongin, KR;

Kil-Won Lee, Yongin, KR;

Dong-Hyun Lee, Yongin, KR;

Sang-Yon Yoon, Yongin, KR;

Jong-Ryuk Park, Yongin, KR;

Bo-Kyung Choi, Yongin, KR;

Maxim Lisachenko, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming a polycrystalline silicon layer and an atomic layer deposition apparatus used for the same. The method includes forming an amorphous silicon layer on a substrate, exposing the substrate having the amorphous silicon layer to a hydrophilic or hydrophobic gas atmosphere, placing a mask having at least one open and at least one closed portion over the amorphous silicon layer, irradiating UV light toward the amorphous silicon layer and the mask using a UV lamp, depositing a crystallization-inducing metal on the amorphous silicon layer, and annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer. This method and apparatus provide for controlling the seed position and grain size in the formation of a polycrystalline silicon layer.


Find Patent Forward Citations

Loading…