The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2013

Filed:

Apr. 06, 2011
Applicants:

Daniel M. Dreps, Georgetown, TX (US);

Kyu-hyoun Kim, Mount Kisco, NY (US);

Michael A. Sorna, Hopewell Junction, NY (US);

Glen A. Wiedemeier, Austin, TX (US);

Inventors:

Daniel M. Dreps, Georgetown, TX (US);

Kyu-hyoun Kim, Mount Kisco, NY (US);

Michael A. Sorna, Hopewell Junction, NY (US);

Glen A. Wiedemeier, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); G06F 13/38 (2006.01);
U.S. Cl.
CPC ...
G06F 13/385 (2013.01); G06F 1/10 (2013.01);
Abstract

A multi-use physical (PHY) architecture that includes a PHY connection that includes one or more bit lines and that is communicatively coupled to a first processor. The PHY connection is configurable to carry signals between the first processor and a second processor, or between the first processor and a memory. The one or more bit lines are configured to carry signals bi-directionally at a first voltage when the PHY connection is configured to carry signals between the first processor and the memory. The one or more bit lines are configured to carry signals uni-directionally at a second voltage when the PHY connection is configured to carry signals between the first processor and the second processor. The second voltage is different than the first voltage.


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