The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2013

Filed:

Jan. 27, 2009
Applicants:

James M. Simkins, Park City, UT (US);

Alvin Y. Ching, Sunnyvale, CA (US);

John M. Thendean, Pleasanton, CA (US);

Vasisht M. Vadi, San Jose, CA (US);

Chi Fung Poon, San Jose, CA (US);

Muhammad Asim Rab, Campbell, CA (US);

Inventors:

James M. Simkins, Park City, UT (US);

Alvin Y. Ching, Sunnyvale, CA (US);

John M. Thendean, Pleasanton, CA (US);

Vasisht M. Vadi, San Jose, CA (US);

Chi Fung Poon, San Jose, CA (US);

Muhammad Asim Rab, Campbell, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/50 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.


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