The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2013
Filed:
Apr. 06, 2010
Mitsuhiro Ogai, Yokohama, JP;
Hirokazu Yamazaki, Yokohama, JP;
Keizo Morita, Yokohama, JP;
Kazuaki Yamane, Yokohama, JP;
Yasuhiro Fujii, Yokohama, JP;
Kazuaki Takai, Yokohama, JP;
Shoichiro Kawashima, Yokohama, JP;
Mitsuhiro Ogai, Yokohama, JP;
Hirokazu Yamazaki, Yokohama, JP;
Keizo Morita, Yokohama, JP;
Kazuaki Yamane, Yokohama, JP;
Yasuhiro Fujii, Yokohama, JP;
Kazuaki Takai, Yokohama, JP;
Shoichiro Kawashima, Yokohama, JP;
Fujitsu Semiconductor Limited, Yokohama, JP;
Abstract
A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.