The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8541827 B1

Expired

Date of Patent:

Sep. 24, 2013

Filed:

Oct. 16, 2012

Semiconductor memory device including multi-layer gate structure

Applicant:

Toshitake Yaegashi, Yokohama, JP;

Inventor:

Toshitake Yaegashi, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Attorney:

Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Hoai V Pham

Int. Cl.

CPC ...

H01L 27/108 (2006.01); H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/119 (2006.01);

U.S. Cl.

CPC ...

Abstract

A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.

Find Patent Forward Citations

Yaegashi, Toshitake. (2013). Semiconductor memory device including multi-layer gate structure (U.S. Patent No. 8541827). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8541827

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