The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2013

Filed:

Jan. 03, 2011
Applicants:

Song-yi Yang, Seoul, KR;

Seung-pil Chung, Seoul, KR;

Dong-hyun Kim, Hwaseong-si, KR;

O-ik Kwon, Seongnam-si, KR;

Hong Cho, Yongin-si, KR;

Inventors:

Song-yi Yang, Seoul, KR;

Seung-pil Chung, Seoul, KR;

Dong-hyun Kim, Hwaseong-si, KR;

O-ik Kwon, Seongnam-si, KR;

Hong Cho, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 21/302 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device and a method of forming patterns on a semiconductor device are disclosed. The semiconductor device may include high-density patterns with a minimum size that may be less the resolution limit of a photolithography process, and may have a substrate including a memory cell region and an adjacent connection region, a plurality of first conductive lines extending from the memory cell region to the connection region in a first direction, a plurality of second conductive lines connected from respective first conductive lines to a plurality of pads having a width equal to twice the width of each of the first conductive lines. The method may include two levels of spacer formation to provide sub resolution line widths and spaces as well as selected multiples of the minimum line widths and spaces.


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