The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2013
Filed:
Mar. 26, 2008
Erik Berg, Lidingo, SE;
Erik Hagersten, Uppsala, SE;
Hakan Zeffer, Santa Clara, CA (US);
Magnus Vesterlund, Stockholm, SE;
Mats Nilsson, Taby, SE;
Mikael Petterson, Koping, SE;
Erik Berg, Lidingo, SE;
Erik Hagersten, Uppsala, SE;
Hakan Zeffer, Santa Clara, CA (US);
Magnus Vesterlund, Stockholm, SE;
Mats Nilsson, Taby, SE;
Mikael Petterson, Koping, SE;
Rogue Wave Software, Inc., Boulder, CO (US);
Abstract
A system, method, and computer program product that captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted. Reuse distance for one memory operation may be measured as the number of memory operations that have been performed since the memory object it accesses was last accessed. Separate call stacks leading up to the same memory operation are identified and statistics are separated for the different call stacks. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations. Methods for assessing cache utilization as well as parallel execution are covered. The method includes modeling multithreaded memory systems and detecting false sharing coherence misses.