The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2013

Filed:

Jun. 22, 2011
Applicants:

Byoungsul Kim, Suwon-si, KR;

Hakyong Lee, Suwon-si, KR;

Jun-ho JO, Hwaseong-si, KR;

Kyu-min Park, Bucheon-si, KR;

Inventors:

Byoungsul Kim, Suwon-si, KR;

Hakyong Lee, Suwon-si, KR;

Jun-Ho Jo, Hwaseong-si, KR;

Kyu-Min Park, Bucheon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A test mode control circuit is provided to strictly allow entry into a test mode or prevent a boot failure from occurring during a boot operation for a built-in parallel bit test. The test mode control circuit includes a latch, a real entry signal detector, an entry determinator, and a mode control signal generator. When a real entry signal is detected, the entry signal determinator generates an entry determination signal and a test mode control signal is obtained from the mode control signal generator.


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