The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2013

Filed:

Sep. 25, 2009
Applicants:

Jeffrey Paquette, Newton, MA (US);

Scott R. Cheyne, Brookline, MA (US);

Joseph R. Ellsworth, Pelham, NH (US);

Michael P. Martinez, Worcester, MA (US);

Michael R. Trahan, Northbridge, MA (US);

Inventors:

Jeffrey Paquette, Newton, MA (US);

Scott R. Cheyne, Brookline, MA (US);

Joseph R. Ellsworth, Pelham, NH (US);

Michael P. Martinez, Worcester, MA (US);

Michael R. Trahan, Northbridge, MA (US);

Assignee:

Raytheon Company, Waltham, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/20 (2006.01); F28F 7/00 (2006.01); H01Q 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A thermal interface includes a plurality of elevated regions and a plurality of mechanical tolerance circuits coupled to the plurality of elevated regions. The thermal interface is configured to be disposed between an array of heat generating elements and a heat sink with each of the plurality of elevated regions thermally coupled to a corresponding one or more of the array of heat generating elements. In one embodiment, the thermal interface provides a thermal path between a printed wiring board having a plurality of flip-chip circuit components disposed on an external surface thereof and a heat sink disposed over the flip-chip circuit components.


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