The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2013
Filed:
Dec. 29, 2008
Dipankar Bhattacharya, Macungie, PA (US);
Makeshwar Kothandaraman, Whitehall, PA (US);
John C. Kriz, Palmerton, PA (US);
Bernard L. Morris, Emmaus, PA (US);
Jeffrey J. Nagy, Allentown, PA (US);
Peter J. Nicholas, Philadelphia, PA (US);
Dipankar Bhattacharya, Macungie, PA (US);
Makeshwar Kothandaraman, Whitehall, PA (US);
John C. Kriz, Palmerton, PA (US);
Bernard L. Morris, Emmaus, PA (US);
Jeffrey J. Nagy, Allentown, PA (US);
Peter J. Nicholas, Philadelphia, PA (US);
Agere Systems LLC, Allentown, PA (US);
Abstract
A voltage translator circuit () includes an input stage () adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch () adapted for connection to a second voltage supply (VDD) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp () coupled between the input stage () and the latch (). The voltage clamp () is operative to set a maximum voltage across the latch () to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit () generates a first output signal (II) at a junction between the latch () and the voltage clamp (). The voltage translator circuit generates a second output signal () at a junction between the voltage clamp () and the input stage ().