The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2013
Filed:
Oct. 07, 2011
Jonathan C Park, San Jose, CA (US);
Salah M Werfelli, Morgan Hill, CA (US);
Weizhi Kang, Kelantan, MY;
Wan Tat Hooi, Perak, MY;
Kok Siong Tee, Penang, MY;
Jeremy Jia Jian Lee, Perak, MY;
Jonathan C Park, San Jose, CA (US);
Salah M Werfelli, Morgan Hill, CA (US);
WeiZhi Kang, Kelantan, MY;
Wan Tat Hooi, Perak, MY;
Kok Siong Tee, Penang, MY;
Jeremy Jia Jian Lee, Perak, MY;
Baysand Inc., San Jose, CA (US);
Abstract
Systems and methods are disclosed for forming a custom integrated circuit (IC) with a first fixed (non-programmable) region on a wafer with non-customizable mask layers, wherein the first fixed region includes multiplicities of transistors and a first interconnect layer and a second interconnect layer above the first interconnect layer which form base cells; and a programmable region above the first fixed region with customizable mask layers, wherein at least one mask layer in the programmable region is coupled to the second interconnect layer which provides electrical access to all transistor nodes of the base cells and wherein the programmable region comprises a third interconnect layer coupled to the customizable mask layers to customize the IC. A second fixed region may be formed above the programmable region to provide multiple fixed regions and reduce the number of required masks in customizing the custom IC.