The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2013
Filed:
Dec. 01, 2011
Kenneth William Ferguson, Burnaby, CA;
Steven Yu Peng NG, Vancouver, CA;
Bradley Burke, Roseville, CA (US);
Michel Duchesneau, Mirabel, CA;
Aaron John Dennis, Saskatoon, CA;
Philip Lyon Northcott, Coquitlam, CA;
Kenneth David Wagner, West Vancouver, CA;
Kenneth William Ferguson, Burnaby, CA;
Steven Yu Peng Ng, Vancouver, CA;
Bradley Burke, Roseville, CA (US);
Michel Duchesneau, Mirabel, CA;
Aaron John Dennis, Saskatoon, CA;
Philip Lyon Northcott, Coquitlam, CA;
Kenneth David Wagner, West Vancouver, CA;
PMC-Sierra US, Inc., Sunnyvale, CA (US);
Abstract
The present disclosure provides systems and methods for testing an integrated circuit or device under test (DUT). A DUT of the present invention has a plurality of scan chains, a plurality of shift register elements each associated with a respective one of the scan chains, and a programmable switch matrix to configure shift register elements of a subset of the plurality of shift register elements to cause one shift register element of the subset to receive an interleaved test sequence, and to cause the interleaved test sequence to be shifted to other shift register elements in the subset, and to input deinterleaved test sequences to scan chains associated with the subset.