The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2013
Filed:
Nov. 15, 2006
Lucian Codrescu, Austin, TX (US);
William C. Anderson, Austin, TX (US);
Suresh Venkumahanti, Austin, TX (US);
Louis Achille Giannini, Berwyn, IL (US);
Manojkumar Pyla, San Diego, CA (US);
Xufeng Chen, San Diego, CA (US);
Lucian Codrescu, Austin, TX (US);
William C. Anderson, Austin, TX (US);
Suresh Venkumahanti, Austin, TX (US);
Louis Achille Giannini, Berwyn, IL (US);
Manojkumar Pyla, San Diego, CA (US);
Xufeng Chen, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Trusted and untrusted debugging operational control occurs in operating a core processor associated with the digital signal processor. A debugging process within a debugging mechanism associates with the core processor. The core processor process determines the origin of debugging control as trusted debugging control or untrusted debugging control. In the event of trusted debugging control, the core processor process provides to the trusted debugging control a first set of features and privileges. Alternatively, in the event that debugging control is untrusted debugging control, the core processor process provides the untrusted debugging control a second restricted set of features and privileges, all for maintaining security and proper operation of the core processor process.