The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2013

Filed:

May. 28, 2011
Applicants:

Venkat Rao Vallapaneni, Bangalore, IN;

Srinivasa Rao Kothamasu, Addanki Post & Mandal, IN;

Sakthivel Komarasamy Pullagoundapatti, Bangalore, IN;

Inventors:

Venkat Rao Vallapaneni, Bangalore, IN;

Srinivasa Rao Kothamasu, Addanki Post & Mandal, IN;

Sakthivel Komarasamy Pullagoundapatti, Bangalore, IN;

Assignee:

LSI Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/364 (2006.01);
U.S. Cl.
CPC ...
G06F 13/364 (2013.01);
Abstract

A system and method for allocating transaction ID in a system with a plurality of processing modules is disclosed. In one embodiment, a method for assigning transaction ID to a processing module in a network on a chip system (NOCS) with a plurality of processing modules is disclosed. An address space is provided to each of the processing modules. A portion of the address space is selected. A subset of the selected portion of the address space for each of the processing module is selected as Valid Bits. The Valid Bits of the processing module is associated to a transaction ID.


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