The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2013
Filed:
Feb. 12, 2007
Srisai R. Seethamraju, Nashua, NH (US);
Jerrell P. Hein, Driftwood, TX (US);
Kenneth Kin Wai Wong, Weston, MA (US);
Qicheng Yu, Nashua, NH (US);
Srisai R. Seethamraju, Nashua, NH (US);
Jerrell P. Hein, Driftwood, TX (US);
Kenneth Kin Wai Wong, Weston, MA (US);
Qicheng Yu, Nashua, NH (US);
Silicon Laboratories Inc., Austin, TX (US);
Abstract
A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.