The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2013

Filed:

May. 29, 2012
Applicants:

Tzu-cheng Yang, New Taipei, TW;

Chien-hsi Lee, Miaoli County, TW;

Inventors:

Tzu-Cheng Yang, New Taipei, TW;

Chien-Hsi Lee, Miaoli County, TW;

Assignee:

NOVATEK Microelectronics Corp., Hsinchu Science Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A delay lock loop circuit includes a voltage controlled delay line for generating a plurality of specific phase differential signals and a feedback signal according to an input clock source and a control voltage, a detector for comparing at least one of phases and frequencies of the input clock source and the feedback signal to generate at least one detection signal, a charge pump for generating the control voltage according to the at least one detection signal, and a phase selection buffer for generating the output clock source according to the plurality of specific phase differential signals, wherein each of the plurality of specific phase differential signals includes at least a non-inversion signal and an inversion signal, and the feedback signal is the inversion signal of one of the plurality of specific phase differential signals.


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