The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2013

Filed:

Nov. 10, 2009
Applicants:

Rinze Ida Mechtildis Peter Meijer, Herkenbosch, NL;

Luis Elvira Villagra, Maastricht, NL;

Inventors:

Rinze Ida Mechtildis Peter Meijer, Herkenbosch, NL;

Luis Elvira Villagra, Maastricht, NL;

Assignee:

NXP, B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 19/0175 (2006.01); H03L 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is an integrated circuit () comprising a plurality of cores (), at least some of the cores being located in different power domains (VDD, VDD), each core being surrounded by a test wrapper () comprising a plurality of wrapper cells (), wherein each of said test wrappers are located in a single power domain (VDD) and each plurality of wrapper cells comprises wrapper output cells () each arranged to output a signal from its associated core, each of said wrapper output cells comprising an output level shifter () for shifting the voltage of said signal to the voltage of the single power domain (VDD). A method for testing such an IC and standard library cells for designing such an IC are also disclosed.


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