The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8530900 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 10, 2013

Filed:

Jun. 13, 2012
Applicants:

Mitsutaka Matsumoto, Kyoto, JP;

Yuta Sugawara, Osaka, JP;

Inventors:

Mitsutaka Matsumoto, Kyoto, JP;

Yuta Sugawara, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
Abstract

Preparing a substrate; forming a plurality of gate electrodes above the substrate; forming a gate insulating layer above the gate electrodes; forming an amorphous silicon layer above the gate insulating layer; forming crystalline silicon layer regions by irradiating the amorphous silicon layer in regions above the gate electrodes with a laser beam having a wavelength from 473 nm to 561 nm so as to crystallize the amorphous silicon layer in the regions above the gate electrodes, and forming an amorphous silicon layer region in a region other than the regions above the gate electrodes; and forming source electrodes and drain electrodes above the crystalline silicon layer regions are included, and a thickness of the gate insulating layer and a thickness of the amorphous silicon layer satisfy predetermined expressions.


Find Patent Forward Citations

Matsumoto, Mitsutaka. (2013). Method for selectively forming crystalline silicon layer regions above gate electrodes (U.S. Patent No. 8530900). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8530900

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