The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2013
Filed:
Dec. 21, 2010
Yoshiyuki Harumoto, Osaka, JP;
Takeshi Hara, Osaka, JP;
Tohru Okabe, Osaka, JP;
Takeshi Yaneda, Osaka, JP;
Tetsuya Aita, Osaka, JP;
Tsuyoshi Inoue, Osaka, JP;
Michiko Takei, Osaka, JP;
Yoshiyuki Harumoto, Osaka, JP;
Takeshi Hara, Osaka, JP;
Tohru Okabe, Osaka, JP;
Takeshi Yaneda, Osaka, JP;
Tetsuya Aita, Osaka, JP;
Tsuyoshi Inoue, Osaka, JP;
Michiko Takei, Osaka, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
The present invention has an object of providing a TFT in which generation of an OFF current is reduced by an efficient manufacturing method. A thin film transistoraccording to the present invention has a gate electrodeformed on a substrate, an insulating layerformed on the gate electrode, a microcrystalline amorphous silicon layerand an amorphous silicon layerthat are formed on the insulating layer, a semiconductor layercontaining an impurity formed on the amorphous silicon layer, and a source electrodeA and a drain electrodeB that are formed on the semiconductor layercontaining an impurity. The microcrystalline amorphous silicon layerand the semiconductor layercontaining an impurity are connected to each other through the amorphous silicon layerwithout being in direct contact with each other.