The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2013

Filed:

Jun. 30, 2006
Applicants:

Yuichi Nasu, Kanagawa, JP;

Hirotaka Katou, Kanagawa, JP;

Kazuhiro Narahara, Kanagawa, JP;

Hideyuki Matsunaga, Kanagawa, JP;

Inventors:

Yuichi Nasu, Kanagawa, JP;

Hirotaka Katou, Kanagawa, JP;

Kazuhiro Narahara, Kanagawa, JP;

Hideyuki Matsunaga, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05B 3/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and an apparatus for manufacturing a semiconductor wafer are provided for improving a quality of the semiconductor wafer, and further, for improving a quality of a semiconductor device manufactured by using the semiconductor wafer, by preventing warping from being generated at a stage of a placing step, at the time of performing heat treatment to a semiconductor wafer substrate. The placing process is performed by a placing means so that a time when a temperature difference between a wafer front surface temperature and a wafer rear surface temperature becomes maximum, and a time when warping is generated in the wafer are prior to a time when the wafer is brought into contact with lift pins or a susceptor (i.e., a time after the temperature is at an upper limit value of an infrared temperature region at 600° C.), and the lift pins are brought into contact with the wafer rear surface.


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