Methods of fabricating microelectronic memory devices having flat stopper layers

Abstract

Memory devices comprise a microelectronic substrate including a cell array region and a peripheral region adjacent the cell array region, the cell array region including therein an array of memory cells and the peripheral region including therein peripheral circuits for the array of memory cells, the microelectronic substrate including a lower layer that extends across the cell array region and across the peripheral region and that includes a flat outer surface from the cell array region to the peripheral region. A signal transfer conductor layer extends in the cell array region beneath the flat outer surface of the lower layer and extends in the peripheral region above the flat outer surface of the lower layer. An insulating layer is provided on the lower layer, the insulating layer extending across the cell array region and the peripheral region and also including a flat outer surface from the cell array region to the peripheral region. A flat stopper layer is provided on the flat outer surface of the insulating layer and extending across the cell array region and the peripheral region. Finally, an array of memory cell capacitor storage nodes is provided in the cell array region that extend beyond the flat stopper layer and that penetrate through the flat stopper layer and the insulating layer. Related methods are also provided.