The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2013
Filed:
Nov. 22, 2010
Gianluca Boselli, Plano, TX (US);
Charvaka Duvvury, Plano, TX (US);
Gianluca Boselli, Plano, TX (US);
Charvaka Duvvury, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An integrated circuit () formed at a semiconducting surface of a substrate including a common p-layer () includes functional circuitry () formed on the p-layer () including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (). At least one ESD protection cell (in more detail) is connected to at least one of the plurality of terminals of the functional circuitry (). The protection cell includes at least a first Nwell () formed in the p-layer (), a p-doped diffusion () within the first Nwell () to form at least one Nwell diode comprising an anode () and a cathode (). An NMOS transistoris formed in or on the p-layer () comprising a n+ source (), n+ drain () and a channel region comprising a p-region () between the source and drain, and a gate electrode () on a gate dielectric () on the channel region. The terminal of the functional circuit (, PAD) is coupled to the cathode () of the Nwell diode, and the anode () of the Nwell diode is connected in series with a path from the drain () to the source () of the NMOS transistor ().