The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2013

Filed:

Nov. 01, 2011
Applicants:

Richard G. Roybal, Arlington, TX (US);

Shariq Arshad, Murphy, TX (US);

Shaoping Tang, Allen, TX (US);

James Fred Salzman, Anna, TX (US);

Inventors:

Richard G. Roybal, Arlington, TX (US);

Shariq Arshad, Murphy, TX (US);

Shaoping Tang, Allen, TX (US);

James Fred Salzman, Anna, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/70 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming an integrated circuit (IC) includes providing a substrate having a topside semiconductor surface, wherein the topside semiconductor surface includes at least one of N+ buried layer regions and P+ buried layer regions. An epitaxial layer is grown on the topside semiconductor surface. Pwells are formed in the epitaxial layer. Nwells are formed in the epitaxial layer. NMOS devices are formed in and over the pwells, and PMOS devices are formed in and over the nwells.


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