The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2013
Filed:
Jan. 07, 2013
Chetan Verma, Noida, IN;
Amit Roy, Greater Noida, IN;
Vijay Tayal, Jodhpur, IN;
Freescale Semiconductor, Inc, Austin, TX (US);
Abstract
A method and system for reducing power consumption of an electronic circuit design using an EDA tool includes generating a look-up table (LUT) that stores a mapping between a type, a predetermined optimum power input transition time, and at least one characteristic corresponding to each digital logic element present in a cell library of the EDA tool. An input transition time of a first digital logic element is determined. Then, the first logic element is replaced with a second logic element if the input transition time and the predetermined optimum power input transition time of the first logic element are not equal. The second logic element may be replaced with a third logic element if a timing delay of the second logic element is greater than a timing delay of the first logic element.