The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8527826 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 03, 2013

Filed:

Nov. 07, 2011
Applicants:

Nutan J. P. Kumar, Bangalore, IN;

Srinivas V. N. Polisetty, Bangalore, IN;

Inventors:

Nutan J. P. Kumar, Bangalore, IN;

Srinivas V. N. Polisetty, Bangalore, IN;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A computer-implemented method of verifying logic in a simulation-based behavioral latch model by performing actions including: inserting a value checking module in the behavioral latch model, the value checking module connected to one of a set of latches outside of a scan chain within the behavioral latch model; comparing a value of the one of the set of latches outside of the scan chain with a delta value for the one of the set of latches outside of the scan chain; and providing an error message in response to determining the value and the delta value are distinct.


Find Patent Forward Citations

Kumar, Nutan J. P.. (2013). Logic corruption verification (U.S. Patent No. 8527826). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8527826

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