The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2013

Filed:

Nov. 12, 2010
Applicants:

John A. Dibartolomeo, Providence, RI (US);

Kevin Hudson, Corona, CA (US);

Gary T. Hufton, Corbett, OR (US);

Peter P. Kral, Irvine, CA (US);

Ajay P. Mishra, Irvine, CA (US);

Huan V. Nguyen, Anaheim, CA (US);

Francis W. Walker, Jr., Mission Viejo, CA (US);

Inventors:

John A. DiBartolomeo, Providence, RI (US);

Kevin Hudson, Corona, CA (US);

Gary T. Hufton, Corbett, OR (US);

Peter P. Kral, Irvine, CA (US);

Ajay P. Mishra, Irvine, CA (US);

Huan V. Nguyen, Anaheim, CA (US);

Francis W. Walker, Jr., Mission Viejo, CA (US);

Assignee:

Invensys Systems, Inc., Foxboro, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G21C 15/00 (2006.01); G21C 19/28 (2006.01); G06F 13/368 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a nuclear process control system, a priority logic module (PLM) is provided. The priority logic module comprises a plurality of input ports, each input port associated with one of a plurality of priorities, a plurality of output ports, and a test mode select port associated with a test mode select signal. The test mode select signal selects one of a normal mode or test mode, each mode being associated with matching signals received by the input ports to signals sent by the output ports. The priority logic module further comprises a configurable priority logic circuit, wherein the priority logic circuit maps one of the input ports to one of the output ports.


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