The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2013
Filed:
Oct. 28, 2010
Lisa H. Karlin, Chandler, AZ (US);
Hemant D. Desai, Gilbert, AZ (US);
Lisa H. Karlin, Chandler, AZ (US);
Hemant D. Desai, Gilbert, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A disclosed semiconductor fabrication process includes forming a first bonding structure on a first surface of a cap wafer, forming a second bonding structure on a first surface of a device wafer, and forming a device structure on the device wafer. One or more eutectic flow containment structures are formed on the cap wafer, the device wafer, or both. The flow containment structures may include flow containment micro-cavities (FCMCs) and flow containment micro-levee (FCMLs). The FCMLs may be elongated ridges overlying the first surface of the device wafer and extending substantially parallel to the bonding structure. The FCMLs may include interior FCMLs lying within a perimeter of the bonding structure, exterior FCMLs lying outside of the bonding structure perimeter, or both. When the two wafers are bonded, the FCMLs and FCMCs confine flow of the eutectic material to the region of the bonding structure.