The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2013

Filed:

Aug. 30, 2011
Applicants:

Daisuke Hagishima, Kawasaki, JP;

Atsuhiro Kinoshita, Kamakura, JP;

Kazuya Matsuzawa, Tokyo, JP;

Kazutaka Ikegami, Tokyo, JP;

Yoshifumi Nishi, Yokohama, JP;

Inventors:

Daisuke Hagishima, Kawasaki, JP;

Atsuhiro Kinoshita, Kamakura, JP;

Kazuya Matsuzawa, Tokyo, JP;

Kazutaka Ikegami, Tokyo, JP;

Yoshifumi Nishi, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
Abstract

A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the first and second semiconductor regions.


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