The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2013
Filed:
Jan. 31, 2012
Koichi Arai, Kanagawa, JP;
Yasuaki Kagotoshi, Kanagawa, JP;
Nobuo Machida, Kanagawa, JP;
Natsuki Yokoyama, Mitaka, JP;
Haruka Shimizu, Kodaira, JP;
Koichi Arai, Kanagawa, JP;
Yasuaki Kagotoshi, Kanagawa, JP;
Nobuo Machida, Kanagawa, JP;
Natsuki Yokoyama, Mitaka, JP;
Haruka Shimizu, Kodaira, JP;
Renesas Electronics Corporation, Kawasaki-shi, JP;
Abstract
In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.