The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2013

Filed:

May. 24, 2011
Applicant:

Lester F. Ludwig, Belmont, CA (US);

Inventor:

Lester F. Ludwig, Belmont, CA (US);

Assignee:

Pike Group LLC, Dover, DE (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for implementing electronic circuit modules on elongated structures of semiconducting materials such as carbon nanotubes, graphene nanoribbons, elongated structures of semiconducting polymers or organic semiconductors, other related materials, and printed electronics strip structures is disclosed. The method provides that a plurality of modules can be implemented on distinct adjacent portions of the same elongated structure of semiconducting materials. In powering the modules, each circuit comprises a chain of electronic components arranged so that each end of the chain can function as a power supply terminal. Larger electronic circuit modules can be created from smaller module, and such a modular hierarchy may be extended to an arbitrary number of levels. In a Computer Aided Design (CAD) applications for nanoelectronics and printed electronics, designs for hierarchies electronic circuit modules can be stored and retrieved from one or more a libraries of circuit designs.


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